This invention relates generally to the field of semiconductors and, more particularly, is directed to a semiconductor substrate and process for making such suitable for use in manufacturing a metal oxide semiconductor large scale integrated circuit.
There are two types of semiconductor substrates used in the manufacture of semiconductor devices such as metal oxide semiconductor large scale integrated circuits. One type is known as an intrinsic getter (referred to as IG hereafter) wafer which is a semiconductor wafer having micro defects and a non-defect region near its surface. The second type is a semiconductor wafer having a high resistivity semiconductor layer formed on a low resistivity semiconductor substrate by an epitaxial growth process. The IG wafer, or first type, prevents junction leakage because it inhibits the occurrence of oxidation induced stacking faults (hereafter referred to as "OSF"). The epitaxial wafer, or second type, can decrease the pause time of a semiconductor device because the diffusion length of electrons accidentally generated in the wafer can be decreased.
A semiconductor substrate as shown in FIG. 1 has been proposed which employs the characteristics of both the IG wafer and the epitaxial wafer explained above. The substrate 5 has a low resistivity p.sup.+ -type IG wafer 2 with micro defects 1 in its interior and a high resistivity p-type semiconductor layer 3 grown on the wafer by an epitaxial growth process. In this type of semiconductor substrate, stacking faults and shallow pits in the semiconducor layer 3 are minimized. Thus, the quality of the crystal in layer 3 is improved due to the IG effect.
Since a large potential difference exists at the junction between the p.sup.+ -type IG wafer 2 and the p-type semiconductor layer 3 as shown ink FIG. 2, electrons accidentally generated by x-rays in layer 3 will be repelled at the junction. Thus, the electrons are prevented from diffusing into IG wafer 21. As a result, the semiconductor substrate has a deficiency which is improved by the IG wafer alone without the epitaxial layer.